Location: Albany, NY： Santa Clara, CA： or Tokyo, Japan
Team: Enablement Team ？ Technology Development
Job Description
We are seeking a highly motivated and experienced Senior DFT Engineer to join our Enablement Team supporting the development of advanced semiconductor process technologies at the 2nm node and beyond. You will lead the Design-for-Test (DFT) implementation of large-scale test chips that are critical for enabling and validating our next-generation manufacturing processes.
In this role, you will focus on scan insertion, ATPG, memory BIST, and other DFT methodologies, while also supporting yield analysis and EDA tool collaboration to improve design quality and test efficiency. You will work closely with RTL designers, physical design teams, process integration engineers, and EDA partners to ensure robust DFT infrastructure across our global sites.
Responsibilities
？Define and implement DFT architectures for technology development test chips, focusing on scan, boundary scan, and memory BIST.
？Function and timing verification of implemented DFT circuit, evaluate test coverage with DFT simulation (ATPG, BIST, Fault simuation).
？Propose the best test solution with analysis among test coverage, test cost, test time
？Collaborate with design teams to integrate DFT features from RTL through physical implementation.
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？Develop and validate ATPG and MBIST patterns： support test bring-up and debug on silicon.
？Analyze test data from silicon to identify systematic issues and improve process yield.
？Engage with EDA vendors to evaluate and improve DFT tools and methodologies for advanced nodes.
？Document best practices and contribute to the enablement of scalable DFT flows across future technology nodes.
？Support cross-functional teams spanning design, process, product engineering, and reliability.
事業内容・業種
半導体
【東京／北海道／海外】Test Chip Design Engineer
勤務地
東京都千代田区
給与
※年齢、経験、能力を考慮のうえ、規定により決定
雇用形態
正社員
Key Responsibilities
As a Test Chip Design Engineer, your responsibilities will include:
- Test Chip Physical Design and PPA Analysis:
- Backend (BE) Implementation and Related Flow Development: Drive the full backend implementation flow, from chip-level planning and PG (Power/Ground) network design to floorplan, place, CTS (Clock Tree Synthesis), route, power analysis (PDNA sign-off), and comprehensive physical verification.
- Design Methodology and EDA Tool Utility Development: Develop and enhance design methodologies and associated EDA tool utilities specifically for backend implementation. This includes creating solutions for challenges arising from new process technologies and developing utilities to support our customers effectively.
- Technology Benchmark: Conduct detailed technology benchmarking to thoroughly understand and evaluate the PPA characteristics of new process technologies.
- Collaborate closely with process development teams, circuit design teams, and EDA vendors to define and implement robust design flows.
- Analyze and debug complex physical design issues, including timing, power, and physical verification failures.
- Contribute to the continuous improvement of design processes and methodologies.
- Document design specifications, methodologies, and results clearly and concisely.
事業内容・業種
半導体
