Location: Albany, NY： Santa Clara, CA： or Tokyo, Japan
Team: Enablement Team ？ Technology Development
Job Description
We are seeking a highly motivated and experienced Senior DFT Engineer to join our Enablement Team supporting the development of advanced semiconductor process technologies at the 2nm node and beyond. You will lead the Design-for-Test (DFT) implementation of large-scale test chips that are critical for enabling and validating our next-generation manufacturing processes.
In this role, you will focus on scan insertion, ATPG, memory BIST, and other DFT methodologies, while also supporting yield analysis and EDA tool collaboration to improve design quality and test efficiency. You will work closely with RTL designers, physical design teams, process integration engineers, and EDA partners to ensure robust DFT infrastructure across our global sites.
Responsibilities
？Define and implement DFT architectures for technology development test chips, focusing on scan, boundary scan, and memory BIST.
？Function and timing verification of implemented DFT circuit, evaluate test coverage with DFT simulation (ATPG, BIST, Fault simuation).
？Propose the best test solution with analysis among test coverage, test cost, test time
？Collaborate with design teams to integrate DFT features from RTL through physical implementation.
？
？Develop and validate ATPG and MBIST patterns： support test bring-up and debug on silicon.
？Analyze test data from silicon to identify systematic issues and improve process yield.
？Engage with EDA vendors to evaluate and improve DFT tools and methodologies for advanced nodes.
？Document best practices and contribute to the enablement of scalable DFT flows across future technology nodes.
？Support cross-functional teams spanning design, process, product engineering, and reliability.
事業内容・業種
半導体
