Key Responsibilities
As a Test Chip Design Engineer, your responsibilities will include:
- Test Chip Physical Design and PPA Analysis:
- Backend (BE) Implementation and Related Flow Development: Drive the full backend implementation flow, from chip-level planning and PG (Power/Ground) network design to floorplan, place, CTS (Clock Tree Synthesis), route, power analysis (PDNA sign-off), and comprehensive physical verification.
- Design Methodology and EDA Tool Utility Development: Develop and enhance design methodologies and associated EDA tool utilities specifically for backend implementation. This includes creating solutions for challenges arising from new process technologies and developing utilities to support our customers effectively.
- Technology Benchmark: Conduct detailed technology benchmarking to thoroughly understand and evaluate the PPA characteristics of new process technologies.
- Collaborate closely with process development teams, circuit design teams, and EDA vendors to define and implement robust design flows.
- Analyze and debug complex physical design issues, including timing, power, and physical verification failures.
- Contribute to the continuous improvement of design processes and methodologies.
- Document design specifications, methodologies, and results clearly and concisely.
事業内容・業種
半導体
Rapidus is a leading innovator in cutting-edge digital chip design. We are looking for a talented and experienced Digital Chip Design Engineer to join our team, focusing on Standard Cell Development and Design Technology Co-Optimization (DTCO).
In this role, you will be instrumental in enabling high-performance and low-power digital chips for our next-generation products, by driving the convergence of library design and process technology. You will have the opportunity to work with state-of-the-art technology in a global environment, actively contributing to our advanced product development.
Key Responsibilities:
- Design, evaluate, and optimize standard cell libraries for advanced technology nodes.
- Plan and execute DTCO (Design Technology Co-Optimization) activities, strengthening the collaboration between circuit design and process technology to achieve optimal PPA (Power, Performance, Area) targets.
- Develop and improve custom layout, characterization, and verification flows.
- Design with a keen understanding of design rules, process variations, and reliability requirements.
- Collaborate closely with design teams, process and device development teams, and EDA teams.
- Evaluate and introduce new design methodologies and tools to meet PPA goals.
- Engage in technical discussions and collaborations with IP vendors and EDA venders.
- Document and maintain design data.
事業内容・業種
半導体